An analytical delay reduction strategy for buffer-inserted global interconnects in VDSM technologies

This paper presents innovative closed-form expressions for the propagation delay of buffer-inserted resistive-capacitive global interconnects. These expressions optimize the delay as a function of number of line segments, buffer ratios and line width. Precise simulations have been used to verify the formulation as well as the relationship between each expression. There exists less than 7% error between the derived formulation and the simulation results. Moreover, the authors have used interleaved buffer insertion technique to minimize the effects of crosstalk on the variation of the propagation delay. The new formulation over the interleaved buffer insertion has been simulated using HSPICE to verify the methodology.