Title :
A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS
Author :
Hsu, Cheng-Chung ; Huang, Chen-Chih ; Lin, Ying-Hsi ; Lee, Cha-Cheng ; Soe, Zaw ; Aytur, Turgut ; Yan, Ran-Hong
Author_Institution :
Realtek, Hsinchu
Abstract :
A time-interleaved pipeline ADC is designed with the reconfigurable resolution and sampling rate, Fs, to accommodate different operation scenarios. The main offset and gain mismatches between four sub-ADCs are modulated to the frequency of F/2 by the reference-and opamp-sharing techniques. Fabricated in 90 nm CMOS, the 7 bit ADC has an ENOB of 6.5 at 1.1 GHz sampling rate. The I/Q ADCs totally consume power of 92 mW from a 1.3 V supply.
Keywords :
CMOS integrated circuits; UHF integrated circuits; analogue-digital conversion; CMOS; frequency 1.1 GHz; opamp-sharing techniques; power 92 mW; reconfigurable time-interleaved ADC; reference-sharing techniques; size 92 nm; time-interleaved pipeline ADC; voltage 1.3 V; Bandwidth; Capacitors; Chaos; Clocks; OFDM; Pipelines; Sampling methods; Tellurium; Ultra wideband technology; Voltage; reconfigurable; time-interleaved pipeline ADC;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342768
