Some optimizations of hardware multiplication by constant matrices

Author

Boullis, Nicolas ; Tisserand, Arnaud

Author_Institution

LIP, Ecole Normale Superieure de Lyon, France

fYear

2003

Firstpage

20

Lastpage

27

Abstract

We present some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication (CMM), i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40% area and speed savings are achieved.

Keywords

digital arithmetic; field programmable gate arrays; hardware description languages; logic circuits; matrix multiplication; CMM; FPGA; VHDL generator; automatic circuit generation; common subexpression factorization algorithm; constant matrix multiplication; factorization algorithms; hardware multiplication optimization; Circuits; Coordinate measuring machines; Discrete Fourier transforms; Discrete cosine transforms; Energy consumption; Field programmable gate arrays; Finite impulse response filter; Hardware; Signal processing algorithms; Space exploration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Arithmetic, 2003. Proceedings. 16th IEEE Symposium on

ISSN

1063-6889

Print_ISBN

0-7695-1894-X

Type

conf

DOI

10.1109/ARITH.2003.1207656

Filename

1207656