Title :
A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing
Author :
Bhavnagarwala, Azeez ; Kosonocky, Stephen ; Chan, Yuen ; Stawiasz, Kevin ; Srinivasan, Uma ; Kowalczyk, Steve ; Ziegler, Matt
Author_Institution :
IBM, Yorktown Heights
Abstract :
Combinations of circuit techniques enabling tolerance to Vtau fluctuations in SRAM cell transistors during read or write operations and significant reductions in minimum operating voltage are reported. Implemented in a 9 Kb times 74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST, these techniques, demonstrate VMIN of 0.58 V and 0.40 V/0.54 V for single and dual VDD implementations respectively. The techniques consume a 10-12% overhead in area, improve performance marginally and also enable over 50% reduction in cell leakage with minimal circuit overhead.
Keywords :
CMOS memory circuits; SRAM chips; cellular arrays; silicon-on-insulator; CMOS SRAM cell array; PDSOI CMOS SRAM array; SRAM cell transistors; Vtau fluctuations tolerance; cell leakage reduction; circuit techniques; conventional ABIST; dual VDD implementations; dynamic cell biasing; minimal circuit overhead; minimum operating voltage; read-write operations; single VDD implementations; size 65 nm; voltage 600 mV; CMOS technology; Choppers; Circuits; Clocks; Degradation; Fluctuations; Power supplies; Random access memory; Space vector pulse width modulation; Voltage;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342773
