Fault emulation and test pattern generation using reconfigurable computing

This paper investigates the use of reconfigurable computing and readily available Field Programmable Gate Array (FPGA) platforms to expedite the generation of input-patterns for testing integrated circuits after manufacture. In this paper, we describe our techniques that efficiently identify the fault locations and the most effective input patterns by leveraging the parallel nature of the FPGA hardware. Our result on benchmark circuits show that our approach is able to create the smallest test-set size for detection of nodes stuck-at high or low voltages.