DocumentCode
1571911
Title
Design space exploration using the genetic algorithm
Author
Esbensen, Henrdk ; Kuh, Ernest S.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Volume
4
fYear
1996
Firstpage
500
Abstract
A typical VLSI layout problem involves the simultaneous optimization of a number of competing criteria. Rather than generating a single compromise solution, some recent approaches explicitly explores the design space and outputs a set of alternative solutions, thereby providing explicit information on the possible tradeoffs. This paper discuss the use of genetic algorithms (GAs) for design space exploration and propose a solution set quality measure needed to evaluate the performance of set-generating algorithms. A GA for building-block placement is evaluated using the proposed measure and promising results are obtained
Keywords
VLSI; circuit layout CAD; circuit optimisation; genetic algorithms; integrated circuit layout; VLSI layout problem; building-block placement; design space exploration; genetic algorithm; optimization; set-generating algorithms; Algorithm design and analysis; Cost function; Design optimization; Genetic algorithms; Genetic mutations; Iterative algorithms; Space exploration; Steady-state; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.542010
Filename
542010
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