SAT-based ATPG testing of inter- and intra-gate bridging faults

Author

Nakura, Toru ; Tatemura, Yutaro ; Fey, Görschwin ; Ikeda, Makoto ; Komatsu, Satoshi ; Asada, Kunihiro

Author_Institution

VDEC, Univ. of Tokyo, Tokyo, Japan

fYear

2009

Firstpage

643

Lastpage

646

Abstract

This paper presents an ATPG framework for IDDQ testing of both intra- and inter-gate bridging faults. The framework integrates random simulation and a deterministic stage using Boolean SATisfiability (SAT) as the underlying engine. This decides whether a fault is testable or untestable. In this way, we conduct an exact search for test patterns for IDDQ testing of both intra- and inter-gate bridging fault detection.

Keywords

Boolean functions; automatic test pattern generation; bridge circuits; fault diagnosis; integrated circuit testing; Boolean SATisfiability; IDDQ testing; SAT-based ATPG testing; inter-gate bridging fault detection; intra-gate bridging fault detection; Automatic test pattern generation; Circuit faults; Circuit testing; Electrical fault detection; Engines; Fault detection; Large scale integration; Logic; Test pattern generators; Wires; ATPG; IDDQ; SAT; bridging fault; intra-/inter-gate;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2009. ECCTD 2009. European Conference on

Conference_Location

Antalya

Print_ISBN

978-1-4244-3896-9

Electronic_ISBN

978-1-4244-3896-9

Type

conf

DOI

10.1109/ECCTD.2009.5275065

Filename

5275065

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1571996