Title :
Energy-delay estimation technique for high-performance microprocessor VLSI adders
Author :
Oklobdzija, Vojin G. ; Zeydel, Bart R. ; Dao, Hoang ; Mathew, Sanu ; Krishnamurthy, Ram
Author_Institution :
California Univ., Davis, CA, USA
Abstract :
We motivate the concept of comparing VLSI adders based on their energy-delay trade-offs and present a technique for estimating the energy-delay space of various high-performance VLSI adder topologies. Further, we show that our estimates accurately represent tradeoffs in the energy-delay space for high-performance 32-bit and 64-bit processor adders in 0.13μm and 0.10μm CMOS technologies, with an accuracy of 8% in delay estimates and 20% in energy estimates, compared with simulated data.
Keywords :
CMOS logic circuits; VLSI; adders; delay estimation; 0.10 micron; 0.13 micron; 32 bit; 64 bit; CMOS technology; VLSI adder topology; energy-delay space estimation; energy-delay trade-off; Adders; CMOS technology; Circuit simulation; Circuit topology; Delay estimation; Digital arithmetic; Logic; Microprocessors; Space technology; Very large scale integration;
Conference_Titel :
Computer Arithmetic, 2003. Proceedings. 16th IEEE Symposium on
Print_ISBN :
0-7695-1894-X
DOI :
10.1109/ARITH.2003.1207688
