Energy-delay estimation technique for high-performance microprocessor VLSI adders

We motivate the concept of comparing VLSI adders based on their energy-delay trade-offs and present a technique for estimating the energy-delay space of various high-performance VLSI adder topologies. Further, we show that our estimates accurately represent tradeoffs in the energy-delay space for high-performance 32-bit and 64-bit processor adders in 0.13μm and 0.10μm CMOS technologies, with an accuracy of 8% in delay estimates and 20% in energy estimates, compared with simulated data.