Design of power efficient VLSI arithmetic: speed and power trade-offs

We talk about issues related to performance of arithmetic algorithms when implemented in silicon. Most of the algorithms in use today are based on old and antiquated methods of counting the number of logic gates in the critical path. This produces inaccurate and misleading results. In the course of VLSI processor design it is very important to choose the circuit topology that would yield desired performance for a given power budget. However, the performance and power of a chosen topology will be known only after the fact, i.e. after the design is finished. We motivate the concept of comparing VLSI structures based on their energy-delay trade-offs and we discuss techniques used for estimating the energy-delay space of various high-performance VLSI topologies.