Title :
Hierarchical synthesis based on pareto-optimal fronts
Author :
Roca, E. ; Castro-López, R. ; Fernández, F.V.
Author_Institution :
IMSE, Univ. of Sevilla, Sevilla, Spain
Abstract :
Pareto-optimal fronts have recently arisen as a promising alternative for design space exploration, potentially enabling better and more efficient hierarchical synthesis. This paper reviews the Pareto front generation problem, extends this concept to reconfigurable circuits, and discusses alternative applications to hierarchical synthesis approaches.
Keywords :
Pareto optimisation; integrated circuit design; Pareto front generation problem; Pareto-optimal fronts; design space exploration; hierarchical synthesis; reconfigurable circuits; Capacitors; Circuit simulation; Circuit synthesis; Energy consumption; Iterative methods; Optimization methods; Resistors; Space exploration; System performance; Technological innovation;
Conference_Titel :
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on
Conference_Location :
Antalya
Print_ISBN :
978-1-4244-3896-9
Electronic_ISBN :
978-1-4244-3896-9
DOI :
10.1109/ECCTD.2009.5275085
