Title :
A low power linearity-ratio-independent DAC with application in multi-bit ΔΣ ADCs
Author :
Song, Yu ; Gao, Zhe ; Ignjatovic, Zeljko
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY, USA
Abstract :
A low power linearity-ratio-independent DAC for ΔΣ data converters is proposed in this paper. By using a gain-boosted sub-threshold inverter as an amplifier, circuit power consumption is decreased significantly. The sensitivity of the differential DAC output linearity on circuit mismatches is reduced by using mutually-referred inputs. In a 0.13um CMOS technology, Monte-Carlo analysis and transistor-level simulations show that with 660μW power consumption, the DAC demonstrates 16 bit linearity at an 8MHz output rate. Its differential output swing is about 1.2V with a 1.2V power supply. A multi-bit ΔΣ modulator is designed using the proposed DAC.
Keywords :
CMOS analogue integrated circuits; Monte Carlo methods; amplifiers; delta-sigma modulation; low-power electronics; ΔΣ data converter; CMOS technology; Monte-Carlo analysis; amplifier; circuit mismatches; circuit power consumption; differential DAC output linearity; differential output swing; frequency 8 MHz; gain-boosted sub-threshold inverter; low power linearity-ratio-independent DAC; multibit ΔΣ ADC; multibit ΔΣ modulator; power 660 muW; size 0.13 mum; transistor-level simulation; voltage 1.2 V; Analytical models; Bandwidth; CMOS technology; Circuits; Energy consumption; Inverters; Linearity; Power amplifiers; Power supplies; Voltage;
Conference_Titel :
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-7771-5
DOI :
10.1109/MWSCAS.2010.5548734
