DocumentCode :
1573033
Title :
ConfRes: interactive coding conflict resolver based on core visualisation
Author :
Madalinski, A.
Author_Institution :
Newcastle upon Tyne Univ., UK
fYear :
2003
Firstpage :
243
Lastpage :
244
Abstract :
The tool presented supports manual resolution of coding conflicts in asynchronous circuit specification given as signal transition graphs (STGs) and displays them as partial orders (finite and complete prefixes of STG unfoldings). The manual approach although efficient requires a significant effort from the designer. The tool ConfRes assists the designer by visualising the conflict cores, their superposition and the constraints on signal insertion.
Keywords :
Petri nets; asynchronous circuits; circuit analysis computing; data visualisation; formal specification; ConfRes; STG; core visualisation; interactive coding conflict resolver; signal transition graph; Asynchronous circuits; Circuit synthesis; Displays; Encoding; Explosions; Signal design; Signal resolution; Signal synthesis; State-space methods; Visualization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application of Concurrency to System Design, 2003. Proceedings. Third International Conference on
Print_ISBN :
0-7695-1887-7
Type :
conf
DOI :
10.1109/CSD.2003.1207724
Filename :
1207724
Link To Document :
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