Practical implementation of MTCMOS four-phase dual-rail circuits using standard ASIC flows

High power dissipation due to excessive cell counts in dual-rail asynchronous circuits has been clearly recognized by researchers who are trying to overcome on-chip variation issue with this kind of delay-insensitive models. The multi-threshold-voltage power gating technique is considered as a promising solution and several studies have been made regarding its grain level. However, its application is not as simple as one can imagine. In this paper, we first explain whatever fine-grain or coarse-grain implementation measures widely used in synchronous world are not applicable for asynchronous domain, and then propose a method by controlling placement of sequential elements and tailoring traditional power network to cater for the special scenario. Other practical problems such as translation, interface and back-end methodology are also discussed. All these works are developed with standard-cell-based ASIC design flows so they can be easily adopted and extended.