System architecture and ASICs for a MIMO 3GPP-HSDPA receiver

Author

Davis, L.M. ; Garrett, D.C. ; Woodward, G.K. ; Bickerstaff, M.A. ; Mullany, E.J.

Author_Institution

Bell Labs Res., Lucent Technol., Sydney, NSW, Australia

Volume

2

fYear

2003

Firstpage

818

Abstract

Multiple-input multiple-output (MIMO) technology has been proposed for the high speed downlink packet access (HSDPA) extension to the 3GPP mobile wireless standard to achieve high data throughput with significantly increased spectral efficiency. Data is encoded, interleaved, spread and transmitted over multiple antennas. This paper presents an architecture for a baseband MIMO HSDPA receiver. The architecture is based on two prototype silicon devices that perform MIMO detection and turbo decoding. System simulations prove the high performance potential of the MIMO proposal for HSDPA. Furthermore, the acceptable complexity of both devices demonstrates the practicality of a single chip solution for an HSDPA MIMO receiver.

Keywords

3G mobile communication; MIMO systems; antenna arrays; application specific integrated circuits; decoding; digital integrated circuits; packet radio networks; radio receivers; signal detection; turbo codes; 19.2 Mbit/s; 24 Mbit/s; 3GPP mobile wireless standard; ASIC; MIMO detection; MIMO receiver; data encoding; data spreading; high speed downlink packet access; interleaved data; multiple-input multiple-output; single chip solution; transmitted data; turbo decoding; Baseband; Decoding; Downlink; MIMO; Multiaccess communication; Proposals; Prototypes; Silicon devices; Throughput; Transmitting antennas;

fLanguage

English

Publisher

ieee

Conference_Titel

Vehicular Technology Conference, 2003. VTC 2003-Spring. The 57th IEEE Semiannual

ISSN

1090-3038

Print_ISBN

0-7803-7757-5

Type

conf

DOI

10.1109/VETECS.2003.1207739

Filename

1207739