Energy-efficent, high-performance viterbi ACS unit implementation in 90nm CMOS

Author

Zhang, Ying Ying ; Kocak, Taskin

Author_Institution

Dept. of Electr. & Electron. Eng., Univ. of Bristol, Bristol, UK

fYear

2009

Firstpage

874

Lastpage

877

Abstract

This paper presents a full custom design of an energy-efficient and high-performance add-compare-select (ACS) unit. The ACS circuit is a main building block in a state-parallel architecture based Viterbi decoder implementation. The proposed ACS circuit is implemented in 90 nm CMOS using static logic. A standard ACS circuit is also implemented for comparison purposes. The proposed ACS circuit provides high throughput rate at 617 Mbps with relatively low energy requirement. By using full-custom design paradigm, both ACS blocks are designed with fewer transistors and the resultant layouts occupy smaller areas.

Keywords

CMOS integrated circuits; Viterbi decoding; ACS circuit; ACS unit implementation; CMOS integrated circuit; Viterbi decoder; add-compare-select circuit; building block; size 90 nm; state-parallel architecture; static logic; Adders; CMOS logic circuits; Circuit synthesis; Design engineering; Energy efficiency; Iterative decoding; Parasitic capacitance; Power engineering and energy; Throughput; Viterbi algorithm; add-compare-select circuits; static CMOS; viterbi decoder;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2009. ECCTD 2009. European Conference on

Conference_Location

Antalya

Print_ISBN

978-1-4244-3896-9

Electronic_ISBN

978-1-4244-3896-9

Type

conf

DOI

10.1109/ECCTD.2009.5275124

Filename

5275124