Optimization of PCB via design considering its physical length parameters

This paper presents an investigation in the design of signal vias in multilayered printed circuit boards (PCB) technology, from a signal integrity point of view, for high-speed applications such as processors´ validation platforms. Vias have been designed according with technological design capabilities. Different physical aspect ratios have been considered in the analysis, and then numerical results are compared with S-parameter. Also, time-domain reflectometry (TDR) simulations on representative test structures are analyzed in order to minimize the via discontinuity effect.