Dual-edge triggered energy recovery DCCER flip-flop for low energy applications

Resonant clocking techniques have been shown to achieve significant power reduction compared to square wave clocking. In this paper, we propose a dual-edge triggered Differential Conditional Capturing Energy Recovery (DE-DCCER) flip-flop that allows the clock frequency to be reduced by a factor of two. The proposed flip-flop was tested using STMicroelectronics 90 nm process technology. Simulation results show the correct operation of the dual-edge triggered flip-flop at a frequency of 250 MHz. Modeling the entire system of the clock distribution network with approximately 10,000 flip-flops shows that dual-edge triggering achieves a 56% power reduction in the clock tree and up to 21% total power reduction for the entire system with a penalty of 36.8% increase in area.