Performance of hierarchical multiplexing in ATM switch design

The authors study the delay-throughput characteristics and the buffer requirements associated with hierarchical multiplexing for random and bursty traffic models. The interface data rates to the external lines can be and usually are different from the internal core fabric speed of an asynchronous transfer mode (ATM) switch. As signals are multiplexed inside the switch to higher speeds, the required dimension of the core fabric is reduced, leading to a reduction in physical size, easing of input/output constraints, simpler control, and improved hardware efficiency. The simulation results, for random and bursty traffic models, indicate that this hierarchical multiplexing technique has little impact on the delay-throughput performance. The results also show that a small degree of multiplexing dramatically increases the buffer requirements. However, further multiplexing reduces the amount of buffering down to more acceptable levels