GaSb nanowire pFETs for III-V CMOS

In order to reduce the power consumption, III-V semiconductor materials may be considered to lower the supply voltage. Reports on III-V complementary metal-oxide semiconductor (CMOS) circuitry are scarce and only few devices have been demonstrated to date. We have previously demonstrated III-V CMOS inverters by integrating n-InAs and p-GaSb segments in a single nanowire. Since the design was intended for functionality demonstration, using long gate lengths and a not intentionally doped channel, the operating frequency of the inverters was found to be limited by a large output parasitic capacitance on the pad and the low drive-currents of the GaSb pFET, as compared to the InAs nFET. We have previously shown that the performance of InAs nanowire nFETs can show large values of g_m and I_ON through scaling and device design optimization. We here demonstrate steps to increase the performance of GaSb nanowire pFETs in a similar fashion.