Gate-first process and EOT-scaling of III-V nanowire-based vertical transistors on Si

Non-planar III-V MOSFETs are promising candidate transistor for future n-MOSFET with low power and high speed. Recently, bottom-up In_0.7Ga_0.3As nanowire-channels on Si have been reported. However, the report was limited to large-sized nanowire-channels and EOT is much thicker than the practical devices. In this presentation, we advances the device fabrication by using completely gate-first process and investigate the EOT scaling from 0.70 nm to 2.75 nm. Furthermore, we investigate diameter-scaling of InGaAs/InAlAs/InP core-multishell nanowire-HEMT structure with thin EOT.