A low power CMOS capacitance to pulse duration converter based on a dual clock approach

An interface for integrated capacitive sensors producing a PWM signal is presented. The circuit is based on a recently proposed architecture, which is here improved by the introduction of a double clock strategy allowing jitter reduction. The non idealities of the circuit are investigated in order to obtain design criteria to reduce the jitter and the temperature dependence. The approach is validated with electrical simulations performed on a prototype designed with devices from the 0.32 mum CMOS subset of the STMicroelectronics BCD6s process.