Consideration of Electrical Parasitics in Conjunction with Thermal Behaviour of Power Semiconductor Components

Capacitive and inductive parasitics of every electrically conducting structure are inseparably associated with geometry. Especially in power electronics thermal optimisation along with minimisation of occupied circuit layer area has the demand for a thick metallisation to improve heat spreading. Electrical optimisation by means of minimisation of formation of parasitics instead aims on flat structures. Multi-objective optimisation aims on best compromise solutions. The paper considers a half-bridge configuration of transistors and diodes to investigate aforementioned parasitics by use of simulation. Validation of the results by measurements provide the possibility to use dispersed parameters of simulation results for optimisation purposes.