DocumentCode
1574147
Title
A physical model to predict STT-MRAM performance degradation induced by TDDB
Author
Chih-Hsiang Ho ; Panagopoulos, Georgios D. ; Soo Youn Kim ; Yusung Kim ; Dongsoo Lee ; Roy, Kaushik
Author_Institution
Dept. of ECE, Purdue Univ., West Lafayette, IN, USA
fYear
2013
Firstpage
59
Lastpage
60
Abstract
STT-MRAM is one of the most promising candidates as a next generation nonvolatile memory due to its high speed, low power consumption and superior scalability. While much insight on device physics of MTJ has been gained in recent years, understanding of the impact of TDDB on STT-MRAM performance has been rather limited. In particular, for continuously improving the performance of MTJ, scaling of oxide thickness and increasing voltage drop across MTJ (Vmϋ) are the two main solutions which can degrade the reliability margin. Therefore, an accurate TDDB reliability model with sound underlying physics is needed for evaluation of post-BD reliability of STT-MRAM. In this work, a physical model that captures the random nature of oxide BD time and post-BD current is proposed. Base on the simulation results (validated with experimental results), we suggest new design constraints for better reliability of STT-MRAM.
Keywords
MRAM devices; electric potential; reliability; tunnelling magnetoresistance; MTJ; STT-MRAM; TDDB reliability model; next generation nonvolatile memory; post-BD reliability evaluation; power consumption; scalability; voltage drop; Degradation; Electric breakdown; Predictive models; Reliability; Resistance; Stress; Tunneling magnetoresistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference (DRC), 2013 71st Annual
Conference_Location
Notre Dame, IN
ISSN
1548-3770
Print_ISBN
978-1-4799-0811-0
Type
conf
DOI
10.1109/DRC.2013.6633792
Filename
6633792
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