A 6-bit 130-MS/s low-power tracking ADC in 90 nm CMOS

In this paper, a new design for a low power CMOS current-mode Tracking Analog-to-Digital Converter (ADC) is proposed. A 6-bit ADC, with a maximum acquisition speed of 130 MHz, is implemented in a 1 V analog supply voltage. HSpice simulation results for the proposed tracking ADC verifying the analytical results are also given. It shows that the circuit consumes a static power of 0.63 mW and a dynamic power of 0.49 mW in a commercial 90 nm CMOS process.