Multithread video coding processor for the videophone

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scaler control processor schedules each vector processor independently to achieve real-time video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. Especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithread video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8 μm CMOS cell based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30 Hz