Title :
Processor architecture driven algorithm optimization for fast 2D-DCT
Author_Institution :
Inf. Technol. Res. Labs., NEC Corp., Japan
Abstract :
This paper presents a fast two-dimensional (inverse) discrete cosine transform optimized for software implementation on a RISC microprocessor with an integer multiplier-accumulator (MAC) unit. The number of processor cycles as well as computational error is less than that of the row-column approaches based on fast 1D DCTs. The algorithm is implemented on a 100 MIPS 32-bit scalar RISC microprocessor V830 which has a MAC unit. The 8×8 DCT/IDCT for MPEG1 size (352×240) video with 30 frames/sec can be processed with 38.5 MIPS on V830
Keywords :
discrete cosine transforms; errors; microprocessor chips; pipeline processing; reduced instruction set computing; video coding; 100 MIPS; 32 bit; 38.5 MIPS; MPEG1; RISC microprocessor; V830 scalar processor; computational error; fast 2D-DCT; integer multiplier-accumulator unit; inverse discrete cosine transform; processor architecture driven algorithm optimization; two-dimensional DCT; Computer architecture; Decoding; Digital signal processing; Information technology; Microprocessors; Pipelines; Random access memory; Read-write memory; Reduced instruction set computing; Registers;
Conference_Titel :
VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]
Conference_Location :
Sakai
Print_ISBN :
0-7803-2612-1
DOI :
10.1109/VLSISP.1995.527519
