Title :
A CMOS phase detector for mixed signal ASIC application
Author :
Comer, Donald T.
Author_Institution :
Penn State Harrisburg, Middletown, PA, USA
Abstract :
The author presents a phase detector that is constructed using a type of current mode logic. The resulting design can be fabricated on a conventional CMOS process but exhibits performance that is approximately two times faster than a similar design based upon conventional CMOS logic circuits. At the same time the low voltage swings of the current mode logic produce low parasitic coupling energy, allowing for good compatability with analog cells. The new design is intended for phase locked loop applications n the 25-50 MHz range but may be useful as a standard ASIC building block in other mixed signal applications
Keywords :
CMOS logic circuits; current-mode logic; detector circuits; logic gates; mixed analogue-digital integrated circuits; phase locked loops; 25 to 50 MHz; CMOS phase detector; NOR gate; compatability with analog cells; current mode logic; low parasitic coupling energy; low voltage swings; mixed signal ASIC; phase locked loop; Application specific integrated circuits; CMOS logic circuits; CMOS process; Coupling circuits; Detectors; Low voltage; Phase detection; Phase locked loops; Signal design; Signal detection;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410712
