On the design of low-power CMOS comparators with programmable hysteresis

We compare designs of low-power CMOS comparators with programmable hysteresis. We chose two baseline comparators: a two-stage CMOS op-amp with output inverter and a folded-cascode op-amp with output inverter. To these baseline circuits, we add programmable hysteresis using two methods. The first method uses positive feedback to unbalance the input differential pair. The second method uses positive feedback to steer current through a fixed-value resistor. The comparators were implemented in a 0.5μm CMOS process and operate with ±1.25V supplies. For an input voltage that is 10mV beyond the switching point, the propagation delays of the two-stage comparator with programmable hysteresis are measured as 932ns for the first method biased at 3.1μA and 672ns for the second method biased at 4μA.