Title :
Motorola MC68040 high-speed design using altera EPM5000 erasable programmable logic devices
Author :
Shen, Hui-Chien ; Becker, Stephen M.
Author_Institution :
Sandia Nat. Lab., Albuquerque, NM, USA
Abstract :
Many designs use EPLDs (Erasable Programmable Logic Devices) to implement control logic and state machines. If the design is slow, timing through the EPLD is not crucial so designers often treat the device as a black box. In high speed designs, timing through the EPLD is critical. In these cases a thorough understanding of the device architecture is necessary. Lessons learned in the implementation of a high-speed design using the Altera EPM5130 are discussed
Keywords :
cellular arrays; logic design; microprocessor chips; programmable logic devices; Motorola MC68040; altera EPM5000; block box rules; clock selection; erasable programmable logic devices; expander terms; floorplanning; high-speed design; implementation; internal feedback paths; macrocell layout; prototyping rules; timing; Bidirectional control; Computer architecture; Delay; Feedback; Laboratories; Microprocessors; Programmable logic arrays; Programmable logic devices; Testing; Timing;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410713
