Quantification of interface trap density above threshold voltage by gated hall method in InGaAs buried quantum well MOSFET

Low density of states (DOS) and typically high interface and border trap densities (D<;sub>it<;/sub>) in high mobility group III-V semiconductors provide difficulties in quantification of D<;sub>it<;/sub> near the conduction band edge. The trap response above the threshold voltage can be very fast, and conventional D<;sub>it<;/sub> extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies <;1MHz, cannot distinguish conducting and trapped carriers. In addition, the CV methods have to deal with high dispersion in the accumulation region that makes it a difficult task to measure the true oxide capacitance C<;sub>ox<;/sub> value. Another implication of these properties of III-V interfaces is an ambiguity of determination of electron density in the MOSFET channel. Traditional evaluation of carrier density by integration of the C-V curve, gives significantly overestimated results even if corrected by D<;sub>it<;/sub>. It happens because the CV methods can distinguish free and trap carriers exclusively by their response kinetics, and therefore all trapped electrons responding faster than ~1μs are treated as free electrons. In this work, we are using a gated Hall method [1,2] which allows for direct measurement of free carrier density, and therefore, when combined with CV measurements or electrostatic modeling allows for accurate quantification of D_it spectrum. In addition, the former approach does not need knowledge of C_ox.