Junctionless InGaAs MOSFETs with InAlAs barrier isolation and channel thinning by digital wet etching

The junctionless device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al. in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to conventional inversion-mode MOSFETs. The objective of this work is to implement the junctionless device concept in an In_0.53Ga_0.47As channel, where the SiO₂ insulator in [1] is replaced by a wide bandgap In_0.52Al_0.48As barrier layer. The junctionless device architecture is particularly well suited to III-V channel materials. Firstly, the high doping concentration (N_d) present in the channel of a junctionless MOSFET is less problematic for In_0.53Ga_0.47As than it is for Si. Indeed, the bulk electron mobility in Si is ~100 cm²/V.s at N_d = 1 × 10¹⁹ /cm³ [2], while that in In_0.53Ga_0.47As is ~4,000 cm²/V.s at a similar N_d level [3]. Moreover, the junctionless architecture circumvents the difficulties associated with the implantation [4] or regrowth [5] techniques generally used to form the source/drain (S/D) regions of III-V inversion-mode MOSFETs.