CNTFET SRAM cell design with tolerance to metallic CNTs

Author

Zhang, Zhe ; Delgado-Frias, José G. ; Nyathi, Jabulani

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA

fYear

2010

Firstpage

1105

Lastpage

1108

Abstract

In this study we present a metallic carbon nanotube (CNT) tolerant CNTFET memory. The proposed scheme includes a number of uncorrelated (independent) CNTs in series to form CNTFETs provides tolerance to metallic CNTs. To increase driving capabilities parallel (correlated) transistors are used. In addition spare columns are used to increase the memory array yield. An extremely high probability of having a functional memory array can be obtained with a modest semiconductor CNT probability (P_semi) of 90% and four uncorrelated transistors in series. The probability of having a functional 16×16 memory array is 90.27%, 99.48%, 99.98% and 100% with 0, 1, 2, and 4 spare columns, respectively.

Keywords

SRAM chips; carbon nanotubes; field effect transistors; nanotube devices; CNTFET SRAM cell design; memory array yield; metallic carbon nanotube; parallel transistors; spare columns; CMOS technology; Carbon nanotubes; FinFETs; MOSFETs; Power dissipation; Power system reliability; Random access memory; Semiconductivity; Technological innovation; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on

Conference_Location

Seattle, WA

ISSN

1548-3746

Print_ISBN

978-1-4244-7771-5

Type

conf

DOI

10.1109/MWSCAS.2010.5548846

Filename

5548846