Realization of efficient and low-power parallel face-detection with massive-parallel memory-embedded SIMD matrix

This paper presents an efficient and low-power-consumption parallel face-detection technology based on Haar-like features and implemented with a massive-parallel memory-embedded SIMD matrix. The massive-parallel memory-embedded SIMD matrix architecture has up to 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. For experimented verification of this matrix processing architecture, this parallel Haar-like-feature based face-detection technique has been implemented on an evaluation board and tested in practice. Evaluation results show that a total processing time of about 313 ms at 162 MHz clock frequency and 150 mW power dissipation can be realized. Thus, the reported parallel-face detection method with the massive-parallel memory-embedded SIMD matrix is a practical technology and is a promising solution for real-time mobile multimedia applications.