• DocumentCode
    1575189
  • Title

    Comprehensive trap-level study in SiOx-based resistive switching memory

  • Author

    Yao-Feng Chang ; Ying-Chen Chen ; Ji Li ; Fei Xue ; Yanzhen Wang ; Fei Zhou ; Fowler, B. ; Lee, Jong Chul

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
  • fYear
    2013
  • Firstpage
    135
  • Lastpage
    136
  • Abstract
    The charge-trapping characteristics and trap levels of SiOx-based (TaN/SiO2/n++ Si-substrate) resistive switching memory (RS) have been investigated. Multilevel operation under compliance current control is demonstrated and current transport behavior is analyzed using the normalized conductance of low resistive state (LRS) and high resistive state (HRS). Temperature dependence of I-V characteristics indicates that corresponding trap-level depths and hopping distance are consistent with Frenkel-Poole emission and hopping conductance with voltage-dependent activation energy. In the high-voltage region in LRS, Fowler-Nordheim fitting indicates a weak dependence of tunneling distance on temperature, whereas the effective filament area shows a strong dependence with a calculated filament radius of about 10nm. SEM images of small gaps formed in a planar structure and EDX analysis indicate oxygen-deficient regions within the gap. Our experimental results not only provide additional insights into the trap-level system of SiOx-based RS memory but also help to construct a physical picture for the switching mechanism.
  • Keywords
    Poole-Frenkel effect; X-ray chemical analysis; electric current control; hopping conduction; random-access storage; scanning electron microscopy; silicon compounds; tunnelling; EDX analysis; Fowler-Nordheim fitting; Frenkel-Poole emission; HRS; I-V characteristics; LRS; SEM images; SiOx; TaN-SiO2-Si; charge-trapping; compliance current control; current transport; high resistive state; hopping conductance; hopping distance; low resistive state; oxygen-deficient regions; planar structure; resistive switching memory; trap levels; trap-level study; tunneling distance; voltage-dependent activation energy; Current control; Educational institutions; Fitting; Switches; Temperature dependence; Temperature measurement; Tunneling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Device Research Conference (DRC), 2013 71st Annual
  • Conference_Location
    Notre Dame, IN
  • ISSN
    1548-3770
  • Print_ISBN
    978-1-4799-0811-0
  • Type

    conf

  • DOI
    10.1109/DRC.2013.6633830
  • Filename
    6633830