Design and implementation of LPF IP generator

This work demonstrates the implementation of high-performance visual IP generator for Low Pass (LP) filter using Microsoft Visual Studio 2008. The sum of coefficient product terms is the major part in the LP filter. In the Visual IP Generator, we proposed a novel algorithm that can translate the sum of coefficient product term on behalf of LP filter into the sum of bit shifted term, and then we uses Booth Algorithm to minimize the number of non-zero bit term for reducing adder used. The LP IP generated from this work is also compiled and simulated in Altera Quartus II and compared with the Altera FIR Compiler synthesized LP filter. The comparison results verified our implemented LP filter is better than the LP filter constructed by Altera FIR Compiler. Our design can be accomplished by three stages: set up LP filter parameters, establish the simplified adder tree, and synthesis the VHDL Code. Through these steps, user can save a lot of time and effort in designing and simulation a LP filter using VHDL code.