Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-clocked Systems

In this paper we analyze the effect of dynamic frequency scaling on the complexity of interface design in rationally-related multi-clocked systems. Static timing analysis of rationally-related modules can be used to design robust, error-free interfaces as shown in previous work. In systems with dynamic frequency scaling, however, timing analysis needs to be carried out for each possible frequency. We present a partially automated tool that aids in performing timing analysis and allows interface design to be optimized. We demonstrate the feasibility of our approach and the benefits of tool support in optimizing interface design through a case-study. The interface circuit has been simulated using both SPICE and Verilog.