• DocumentCode
    1575435
  • Title

    PLL frequency synthesizer for TDMA systems

  • Author

    Adachi, Nobuyuh ; Inoue, Akiharu ; Yamashita, Kazuo

  • Author_Institution
    Japan Radio Co. Ltd., Kamifukuoka, Japan
  • fYear
    1995
  • Firstpage
    316
  • Lastpage
    320
  • Abstract
    This paper describes a PLL frequency synthesizer with the high-speed frequency switching for TDMA systems. To achieve the high-speed frequency switching, we have proposed a novel synthesizer of a fractional-N phase locked loop employing a direct variable counter with a multi-modulus prescaler, which can be operated at a higher reference frequency. Additionally to reduce spurious outputs, loop filters are switched from a high-speed loop to a low-speed loop after a constant time. An 800 MHz band PLL frequency synthesizer using these schemes has a frequency switching time of 1.4 ms and a spurious output suppression ratio of -78 dBc at a 50 kHz offset frequency
  • Keywords
    UHF circuits; counting circuits; frequency synthesizers; phase locked loops; prescalers; time division multiple access; 1.4 ms; 50 kHz; 800 MHz; PLL frequency synthesizer; TDMA systems; direct variable counter; fractional-N phase locked loop; frequency switching time; high speed frequency switching; high speed loop; loop filters; low speed loop; multimodulus prescaler; offset frequency; reference frequency; spurious output reduction; spurious output suppression ratio; Counting circuits; Filters; Frequency conversion; Frequency locked loops; Frequency synthesizers; Laboratories; Phase detection; Phase frequency detector; Phase locked loops; Time division multiple access;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Universal Personal Communications. 1995. Record., 1995 Fourth IEEE International Conference on
  • Conference_Location
    Tokyo
  • Print_ISBN
    0-7803-2955-4
  • Type

    conf

  • DOI
    10.1109/ICUPC.1995.496912
  • Filename
    496912