Title :
A CMOS circuit technique for high-speed RAMs
Author :
Alowersson, Jonas
Author_Institution :
Dept. of Comput. Eng., Lund Univ., Sweden
Abstract :
Recently, CMOS circuits at clock speeds normally described with ECL have been demonstrated. The author presents a technique for including RAM structures in such designs. Pipelining the address decoder and integrating a fast sense amplifier in the high-speed CMOS technique allows integration of small RAMs in circuits running at several hundred MHz. A 420 MHz, 32 word by 64-b register file has been designed in 1μm CMOS
Keywords :
CMOS analogue integrated circuits; CMOS memory circuits; application specific integrated circuits; memory architecture; random-access storage; very high speed integrated circuits; 1 micron; 2048 bit; 420 MHz; ASIC; VLSI; address decoder; fast sense amplifier; high-speed CMOS technique; high-speed RAMs; pipelining; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Decoding; Latches; Pipeline processing; Random access memory; Read-write memory; Registers;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410715
