Clocked low power high speed regenerative comparator

Nowadays, designers are working towards for the designs with low power, high speed, low offset voltage and reduced area. For complex designs comparator is one of the basic building blocks in low power applications. Hence designing of a comparator with above mentioned parameters is more challenging one. In this paper, we designed and simulated the different dynamic comparators which are already in use. Based on the results obtained to enhance the parametric values a new dynamic double tail comparator has been proposed and compared with existing comparators in terms of delay, power and slew rate. The modified comparator has edge over the existing types in power consumption. The designs are simulated using 130nm CMOS technology using Mentor Graphics tools for comparisons and analysis.