A survey on VLSI Floorplanning: Its representation and modern approaches of optimization

In the VLSI Physical Design Stage, Floorplanning is an essential step, as it is an effective means to manage circuit design complexity, which is increasing with the advancement in technology. Floorplanning involves determining the locations, shape, size of modules in a chip and as such it estimates the chip area, delay and the wiring congestion, thereby providing a ground work for layout. Computationally, it is a NP hard problem. So many researchers from time to time have suggested various heuristics and metaheuristic approaches for solving the VLSI Floorplan Problem. The Floorplan representation is another important aspect of the Floorplanning Stage. Representations have a great impact on the complexity of the Floorplan design. In this paper, we survey the VLSI Floorplanning problem which includes studying and comparing the different optimization algorithms and the representations involved in the VLSI Floorplanning problem. Additionally we suggest some of the new approaches for solving the floorplanning problem which has not yet been employed in this regard.