Title :
High-order PLL design with constant Phase Margin
Author :
Ugarte, Mikel ; Carlosena, Alfonso
Author_Institution :
Dept. Electr. & Electron. Eng., Univ. Publica de Navarra, Pamplona, Spain
Abstract :
In this paper we describe a novel procedure to design high-type high-order Phase Locked Loops (PLLs) from lower order prototypes, preserving a prescribed Phase Margin (PM). The method builds on a model recently proposed by the authors, and is supported by extensive simulations and experimental results, giving up to a type-III fifth-order PLL with a commercial circuit.
Keywords :
phase locked loops; constant phase margin; high-order PLL design; high-type high-order phase locked loops; type-III fifth-order PLL; Circuit simulation; Equations; Feedback; Filters; Frequency; Phase locked loops; Phase measurement; Poles and zeros; Transfer functions; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-7771-5
DOI :
10.1109/MWSCAS.2010.5548890
