Top down system design using VHDL [FFT system]

The design of a fast Fourier transform (FFT) system is demonstrated. The theory and algorithm of a FFT are introduced. An initial behavior model of the FFT is described in VHDL (VHSIC hardware description language). A behavior architecture, a full pipeline architecture, and a single FPU architecture are compared. These architectures have different characteristics that are revealed in the VHDL simulation. Control path hardware required to implement the butterfly using a single FPU is discussed. The design of the sequence generator is considered in VHDL. The advantages of top down design methodology using VHDL are discussed