Title :
A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method
Author :
Koo, Yido ; Park, Joon-Young ; Park, Joonbae ; Kim, Wonchan
Author_Institution :
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
This paper describes a new DLL structure for an on-chip clock buffer. It achieves acquisition in two steps, coarse and fine tuning. Coarse tuning based on a frequency division method enlarges operating range with bounded acquisition time. It allows small gains in the fine tuning block, which is helpful to jitter suppression. The test chip fabricated in a 0.8 μm CMOS technology operates in the 4-400 MHz range. It has 8.13 ps RMS jitter and dissipates 70.0 mW at 300 MHz
Keywords :
CMOS integrated circuits; buffer circuits; circuit tuning; delay lock loops; frequency dividers; jitter; mixed analogue-digital integrated circuits; 0.8 mum; 4 to 400 MHz; 70 mW; 8.13 ps; CMOS technology; DLL structure; RMS jitter; bounded acquisition time; coarse tuning; fine tuning; frequency division method; jitter suppression; jitter-suppressed delay-locked loop; on-chip clock buffer; operating range; power dissipation; two step acquisition; CMOS technology; Clocks; Counting circuits; Delay effects; Delay lines; Detectors; Frequency conversion; Interpolation; Jitter; Tuning;
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
DOI :
10.1109/ICVC.1999.820925
