Title :
Hardware implementation of Chinese remainder theorem using redundant binary representation
Author :
Ariyama, Kazuhiro ; Toyoshima, Hisamichi
Author_Institution :
Dept. of Electr. Eng., Kanagawa Univ., Yokohama, Japan
Abstract :
In this paper, a new method for hardware implementation of the Chinese Remainder Theorem (CRT). Taking a redundant binary representation, we can realize the CRT algorithm which needs only a one stage carry propagate adder (CPA), though the conventional methods use several stages of CPA. The proposed method can reduce the maximum delay of computing time in RNS-binary conversion
Keywords :
adders; integrated logic circuits; redundant number systems; residue number systems; Chinese remainder theorem; RNS-binary conversion; carry propagate adder; hardware implementation; redundant binary representation; Adders; Arithmetic; Cathode ray tubes; Concurrent computing; Delay effects; Digital signal processing; Dynamic range; Hardware; Read only memory; Signal processing algorithms;
Conference_Titel :
VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]
Conference_Location :
Sakai
Print_ISBN :
0-7803-2612-1
DOI :
10.1109/VLSISP.1995.527526
