Title :
Parameter-driven data path VHDL model generation for ASIC design
Author_Institution :
Intergraph Corp., Huntsville, AL, USA
Abstract :
Previous methods for automatic generation of behavioral VHDL models require an ASIC engineer to have knowledge of particular input techniques such as graphical entry, specialized table, etc. The author presents a new method that takes the user-specified engineering parameters as inputs for the behavioral VHDL model generation. Since it is a common practice for the ASIC engineer to specify circuits using engineering parameters, this parameter-driven method allows an engineer to create a VHDL model quickly and easily. In addition, unlike the previous methods, the proposed method covers a wide range of circuits, including MSI circuits as well as FSM and CMB
Keywords :
application specific integrated circuits; combinational circuits; finite state machines; hardware description languages; high level synthesis; integrated circuit design; integrated logic circuits; ALU; ASIC design; behavioral VHDL model generation; data path VHDL model generation; finite state machine; general combinational block; medium scale integration circuits; parameter-driven method; user-specified engineering parameters; Application specific integrated circuits; Counting circuits; Data engineering; Design engineering; Electronic mail; Guidelines; Knowledge engineering; Productivity; Programmable logic arrays; Registers;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410720
