Development of technology mapping algorithm for CPLD under time constraint

Author

Kim, Jaejin ; Byun, Sangzoon ; Kim, Hiseok

Author_Institution

Dept. of Electron. Eng., Chongju Univ., South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

411

Lastpage

414

Abstract

In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algorithm

Keywords

bin packing; directed graphs; logic design; programmable logic devices; CLB; CPLD; bin packing; directed acyclic graph; logic synthesis; multi-level number; replication; technology mapping algorithm; time constraint; Circuit synthesis; Costs; Delay effects; Digital circuits; Educational institutions; Equations; Field programmable gate arrays; Logic circuits; Logic functions; Time factors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820948

Filename

820948