Improving FSMD design assurance

Author

Auletta, Richard

Author_Institution

Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA

fYear

1993

Firstpage

274

Lastpage

277

Abstract

Assurance is a critical factor in the application of EDA tools to ASIC design. An experimental environment for high-assurance rapid prototyping using an application specific language, formal verification, and circuit synthesis for the design of communicating FSMDs has been successfully demonstrated. Digital design paradigms that consider both the digital and verification domains can integrate symbolic model verification with synthesis to improve and shorten the design cycle

Keywords

application specific integrated circuits; finite state machines; formal verification; hardware description languages; high level synthesis; integrated circuit design; ASIC design; EDA tools; FSMD design assurance; HARP environment; application specific language; bit-serial repeater; cellular processor; circuit synthesis; finite state machine with data path; formal verification; high-assurance rapid prototyping; symbolic model verification; synthesis; Application specific integrated circuits; CMOS technology; Computational modeling; Computer aided manufacturing; Computer integrated manufacturing; Electronic design automation and methodology; Formal verification; Hardware design languages; Integrated circuit manufacture; Modems;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410721

Filename

410721