Design of 2K/4K/8K-point FFT processor based on CORDIC algorithm in OFDM receiver

Author

Park, SangYoon ; Cho, Nam Ik ; Lee, Sang Uk ; Kim, Kichul ; Oh, Jisung

Author_Institution

Sch. of Electr. Eng., Seoul Nat. Univ., South Korea

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

457

Abstract

The architecture and the implementation of a 2K/4K/8K-point complex fast Fourier transform (FFT) processor for an OFDM system are presented. The processor can perform 8K-point FFT every 273 μs, and 2K-point every 68.26 μs at 30 MHz which is enough for the OFDM symbol rate. The architecture is based on the Cooley-Tukey (1965) algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition and shuffle memories are used for the implementation of multi-dimensional transforms. The CORDIC processor is employed for the twiddle factor multiplications in each dimension. A new twiddle factor generation method is also proposed for saving the size of ROM required for storing the twiddle factors

Keywords

CMOS digital integrated circuits; OFDM modulation; digital arithmetic; digital signal processing chips; fast Fourier transforms; radio receivers; read-only storage; 0.18 micron; 30 MHz; CMOS; CORDIC processor; Cooley-Tukey algorithm; DFT; FFT processor architecture; OFDM receiver; OFDM symbol rate; ROM; fast Fourier transform; multi-dimensional transforms; shuffle memories; transposition; twiddle factor generation method; twiddle factor multiplications; Algorithm design and analysis; Demodulation; Digital audio broadcasting; Digital video broadcasting; Discrete Fourier transforms; Discrete transforms; Fast Fourier transforms; OFDM modulation; Read only memory; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and signal Processing, 2001. PACRIM. 2001 IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-7803-7080-5

Type

conf

DOI

10.1109/PACRIM.2001.953668

Filename

953668