Generation of trench dislocation in 0.25 μm logic technology and its elimination

The generation of defect around trench corners has been investigated using delayering and Wright etching method in 0.25 μm logic technology. Process variables impacting the generation of dislocations, including densification of HDP oxide and source/drain (S/D) anneal are studied. It was found that the dislocation density increased abruptly after S/D implantation and post-anneal. Almost all dislocations were detected at trench bottom corners, which correspond to the stress concentrated region. The fact that all etch-pits are discovered at nMOS area without exception implies that the generation of trench dislocations is correlated to the N+S/D implantation. The change of S/D anneal from rapid thermal anneal (RTA) to tube anneal followed by RTA can completely eliminate trench dislocations