Reordering and test pattern generation for reducing launch and capture power

Testing of VLSI circuit aims for high quality screening of the circuits by targeting on performance related faults. Excessive switching in launch and capture operation results in high yield loss. Power management is also a major issue in VLSI design technique. Scan chain reordering method is used to reduce the number of transitions and thus the power consumption gets reduced. Fault injection technique based on the use of hardware description language offer important advantages than other techniques. Saboteurs and mutants methods were important fault injection techniques. By which the number of test pattern generation can be reduced and thus the time for processing was also gets reduced. As this type of technique can be applied during the design phase of the system, which reduces the time-to-market. They provide high controllability and reachability. This technique improves the fault coverage and reduces pattern count. The proposed algorithm is coded in VHDL and simulated using ModelSim and Xilinx ISE 8.1isimulator. The results obtained are compared with the existing version of the technique.